1. Field of the Invention
Embodiments of the present invention generally relate to a method for producing sidewall spacers for gate stacks on semiconductor substrates.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and which cooperate to perform various functions within an electronic device. Such transistors may include complementary metal-oxide-semiconductor (CMOS) field effect transistors.
A CMOS transistor includes a gate structure that is disposed between a source region and a drain region defined in the semiconductor substrate. The gate structure (stack) generally comprises a gate electrode formed on a gate dielectric material. The gate electrode controls a flow of charge carriers, beneath the gate dielectric, in a channel region that is formed between the drain region and the source region, so as to turn the transistor on or off. Typically disposed proximate the gate stack is a spacer layer, which forms a sidewall on either side thereof. Sidewall spacers serve several functions, including, electrically isolating the gate electrode from source and drain contacts or interconnects, protecting the gate stack from physical degradation during subsequent processing steps, and providing an oxygen and moisture barrier to protect the gate metal. One example of such a sidewall spacer arrangement is disclosed in U.S. patent application Ser. No. 10/397,776, filed Mar. 25, 2003.
A conventional gate stack is formed from materials having dielectric constants of less than about 5 (k<5) and is typically protected by a silicon nitride spacer. Further reduction in transistor sizes will likely require gate layers having dielectric constants of greater than 10 (k>10). If the sidewall spacer is then fabricated from a relatively high k (k>7) material, such as silicon nitride, excessive signal crosstalk between adjacent interconnection lines can occur during use of the device containing the completed gate electrode. While ultra-low k materials (k<3) may be employed as a spacer layer, these materials often lack the necessary structural integrity to survive subsequent processing steps and/or requisite oxygen and moisture imperviousness to protect the gate metal from corrosion.
In addition, conventional thermal chemical vapor deposition (CVD) process used to prepare silicon nitride spacer requires high deposition temperature, which is typically greater than 600° C. The nitride spacer deposited at high temperature has very good conformality (e.g. ≧95%); however, the high deposition temperature results in large thermal cycle for the gate device and is not compatible with advanced device manufacturing for 0.09 micron technology and beyond.
Therefore, there is a need for low temperature, and low k sidewall spacers for low k gate stacks, wherein the sidewall spacer possesses the desired physical properties of structural stability and hermeticity.